serial presence detect pc100 unbuffered dimm rev 0.1 apr. 2000 pc100 unbuffered dimm(168pin) spd specification(256mb b-die base) rev. 0.1 apr. 2000
serial presence detect pc100 unbuffered dimm rev 0.1 apr. 2000 m366s3253bt0-c1h/c1l byte # function described function hex value note -1h -1l -1h -1l 0 # of bytes written into serial memory at module manufacturer 128bytes 80h 1 total # of bytes of spd memory device 256bytes (2k- 08h 2 fundamental memory type sdram 04h 3 # of row address on this assembly 13 0dh 1 4 # of column address on this assembly 10 0ah 1 5 # of module rows on this assembly 1 row 01h 6 data width of this assembly 64 bits 40h 7 ...... data width of this assembly - 00h 8 voltage interface standard of this assembly lvttl 01h 9 sdram cycle time @cas latency of 3 10ns 10ns a0h a0h 2 10 sdram access time from clock @cas latency of 3 6ns 6ns 60h 60h 2 11 dimm configuration type non parity 00h 12 refresh rate & type 7.8us, support 82h 13 primary sdram width x8 08h 14 error checking sdram width none 00h 15 minimum clock delay for back-to-back random column address t ccd = 1clk 01h 16 sdram device attributes : burst lengths supported 1, 2, 4, 8 & full 8fh 17 sdram device attributes : # of banks on sdram device 4 banks 04h 18 sdram device attributes : cas latency 2 & 3 06h 19 sdram device attributes : cs latency 0 clk 01h 20 sdram device attributes : write latency 0 clk 01h 21 sdram module attributes non-buffered, non-registered 00h 22 sdram device attributes : general +/- 10% volt- age tolerance, burst read 0eh 23 sdram cycle time @cas latency of 2 10ns 12ns a0h c0h 2 24 sdram access time from clock @cas latency of 2 6ns 7ns 60h 70h 2 25 sdram cycle time @cas latency of 1 - - 00h 00h 26 sdram access time from clock @cas latency of 1 - - 00h 00h 27 minimum row precharge time (=t rp ) 20ns 20ns 14h 14h 28 minimum row active to row active delay (t rrd ) 20ns 20ns 14h 14h 29 minimum ras to cas delay (=t rcd ) 20ns 20ns 14h 14h 30 minimum activate precharge time (=t ras ) 50ns 50ns 32h 32h 31 module row density 1 row of 40h 32 command and address signal input setup time 2ns 2ns 20h 20h 33 command and address signal input hold time 1ns 1ns 10h 10h 34 data signal input setup time 2ns 2ns 20h 20h ? organization : 32mx64 ? composition : 32mx8 * 8 ? used component part # : k4s560832b-tc1h/tc1l ? # of rows in module : 1 row ? # of banks in component : 4 banks ? feature : 1,375mil height & single sided component ? refresh : 8k / 64ms ? contents ;
serial presence detect pc100 unbuffered dimm rev 0.1 apr. 2000 byte # function described function supported hex value note -1h -1l -1h -1l 35 data signal input hold time 1ns 1ns 10h 10h 36~61 superset information (maybe used in future) - 00h 62 spd data revision code pc100 spd spec. ver. 1.2a 12h 63 checksum for bytes 0 ~ 62 - 39h 69h 64 manufacturer jedec id code samsung ceh 65~71 ...... manufacturer jedec id code samsung 00h 72 manufacturing location onyang korea 01h 73 manufacturer part # (memory module) m 4dh 74 manufacturer part # (dimm configuration) 3 33h 75 manufacturer part # (data bits) blank 20h 76 ...... manufacturer part # (data bits) 6 36h 77 ...... manufacturer part # (data bits) 6 36h 78 manufacturer part # (mode & operating voltage) s 53h 79 manufacturer part # (module depth) 3 33h 80 ...... manufacturer part # (module depth) 2 32h 81 manufacturer part # (refresh, # of banks in comp. & interface) 5 35h 82 manufacturer part # (composition component) 3 33h 83 manufacturer part # (component revision) b 42h 84 manufacturer part # (package type) t 54h 85 manufacturer part # (pcb revision & type) 0 30h 86 manufacturer part # (hyphen) " - " 2dh 87 manufacturer part # (power) c 43h 88 manufacturer part # (minimum cycle time) 1 1 31h 31h 89 manufacturer part # (minimum cycle time) h l 48h 4ch 90 manufacturer part # (tbd) blank 20h 91 manufacturer revision code (for pcb) 0 30h 92 ...... manufacturer revision code (for component) b-die (3rd gen.) 42h 93 manufacturing date (week) - - 3 94 manufacturing date (year) - - 3 95~98 assembly serial # - - 4 99~125 manufacturer specific data (may be used in future) undefined - 5 126 system frequency for 100mhz 100mhz 64h 127 pc100 specification details detailed 100mhz information afh adh 128+ unused storage locations undefined - 5 1. the bank select address is excluded in counting the total # of addresses. 2. this value is based on the component specification. 3. these bytes are programmed by code of date week & date year with bcd format. 4. these bytes are programmed by samsung s own assembly serial # system. all modules may have different unique serial #. 5. these bytes are undefined and can be used for samsung s own purpose. note :
serial presence detect pc100 unbuffered dimm rev 0.1 apr. 2000 M366S6453BT0-c1h/c1l byte # function described function supported hex value note -1h -1l -1h -1l 0 # of bytes written into serial memory at module manufacturer 128bytes 80h 1 total # of bytes of spd memory device 256bytes (2k-bit) 08h 2 fundamental memory type sdram 04h 3 # of row address on this assembly 13 0dh 1 4 # of column address on this assembly 10 0ah 1 5 # of module rows on this assembly 2 rows 02h 6 data width of this assembly 64 bits 40h 7 ...... data width of this assembly - 00h 8 voltage interface standard of this assembly lvttl 01h 9 sdram cycle time @cas latency of 3 10ns 10ns a0h a0h 2 10 sdram access time from clock @cas latency of 3 6ns 6ns 60h 60h 2 11 dimm configuration type non parity 00h 12 refresh rate & type 7.8us, support self refresh 82h 13 primary sdram width x8 08h 14 error checking sdram width none 00h 15 minimum clock delay for back-to-back random column address t ccd = 1clk 01h 16 sdram device attributes : burst lengths supported 1, 2, 4, 8 & full page 8fh 17 sdram device attributes : # of banks on sdram device 4 banks 04h 18 sdram device attributes : cas latency 2 & 3 06h 19 sdram device attributes : cs latency 0 clk 01h 20 sdram device attributes : write latency 0 clk 01h 21 sdram module attributes non-buffered, non-registered & redundant addressing 00h 22 sdram device attributes : general +/- 10% voltage tolerance, burst read single bit write precharge all, auto precharge 0eh 23 sdram cycle time @cas latency of 2 10ns 12ns a0h c0h 2 24 sdram access time from clock@cas latency of 2 6ns 7ns 60h 70h 2 25 sdram cycle time @cas latency of 1 - - 00h 00h 26 sdram access time from clock@cas latency of 1 - - 00h 00h 27 minimum row precharge time (=t rp ) 20ns 20ns 14h 14h 28 minimum row active to row active delay (t rrd ) 20ns 20ns 14h 14h 29 minimum ras to cas delay (=t rcd ) 20ns 20ns 14h 14h 30 minimum activate precharge time (=t ras ) 50ns 50ns 32h 32h 31 module row density 2 rows of 256mb 40h 32 command and address signal input setup time 2ns 2ns 20h 20h 33 command and address signal input hold time 1ns 1ns 10h 10h 34 data signal input setup time 2ns 2ns 20h 20h ? organization : 64mx64 ? composition : 32mx8 *16 ? used component part # : k4s560832b-tc1h/tc1l ? # of rows in module : 2 rows ? # of banks in component : 4 banks ? feature : 1,375mil height & double sided component ? refresh : 8k / 64ms ? contents ;
serial presence detect pc100 unbuffered dimm rev 0.1 apr. 2000 byte # function described function supported hex value note -1h -1l -1h -1l 35 data signal input hold time 1ns 1ns 10h 10h 36~61 superset information (maybe used in future) - 00h 62 spd data revision code pc100 spd spec. ver. 1.2a 12h 63 checksum for bytes 0 ~ 62 - 3ah 6ah 64 manufacturer jedec id code samsung ceh 65~71 ...... manufacturer jedec id code samsung 00h 72 manufacturing location onyang korea 01h 73 manufacturer part # (memory module) m 4dh 74 manufacturer part # (dimm configuration) 3 33h 75 manufacturer part # (data bits) blank 20h 76 ...... manufacturer part # (data bits) 6 36h 77 ...... manufacturer part # (data bits) 6 36h 78 manufacturer part # (mode & operating voltage) s 53h 79 manufacturer part # (module depth) 6 36h 80 ...... manufacturer part # (module depth) 4 34h 81 manufacturer part # (refresh, # of banks in comp. & interface) 5 35h 82 manufacturer part # (composition component) 3 33h 83 manufacturer part # (component revision) b 42h 84 manufacturer part # (package type) t 54h 85 manufacturer part # (pcb revision & type) 0 30h 86 manufacturer part # (hyphen) " - " 2dh 87 manufacturer part # (power) c 43h 88 manufacturer part # (minimum cycle time) 1 1 31h 31h 89 manufacturer part # (minimum cycle time) h l 48h 4ch 90 manufacturer part # (tbd) blank 20h 91 manufacturer revision code (for pcb) 0 30h 92 ...... manufacturer revision code (for component) b-die (3rd gen.) 42h 93 manufacturing date (week) - - 3 94 manufacturing date (year) - - 3 95~98 assembly serial # - - 4 99~125 manufacturer specific data (may be used in future) undefined - 5 126 system frequency for 100mhz 100mhz 64h 127 pc100 specification details detailed 100mhz information ffh fdh 128+ unused storage locations undefined - 5 1. the bank select address is excluded in counting the total # of addresses. 2. this value is based on the component specification. 3. these bytes are programmed by code of date week & date year with bcd format. 4. these bytes are programmed by samsung s own assembly serial # system. all modules may have different unique serial #. 5. these bytes are undefined and can be used for samsung s own purpose. note :
serial presence detect pc100 unbuffered dimm rev 0.1 apr. 2000 m374s3253bt0-c1h/c1l byte # function described function supported hex value note -1h -1l -1h -1l 0 # of bytes written into serial memory at module manufacturer 128bytes 80h 1 total # of bytes of spd memory device 256bytes (2k-bit) 08h 2 fundamental memory type sdram 04h 3 # of row address on this assembly 13 0dh 1 4 # of column address on this assembly 10 0ah 1 5 # of module rows on this assembly 1 row 01h 6 data width of this assembly 72 bits 48h 7 ...... data width of this assembly - 00h 8 voltage interface standard of this assembly lvttl 01h 9 sdram cycle time @cas latency of 3 10ns 10ns a0h a0h 2 10 sdram access time from clock @cas latency of 3 6ns 6ns 60h 60h 2 11 dimm configuration type ecc 02h 12 refresh rate & type 7.8 us, support self refresh 82h 13 primary sdram width x8 08h 14 error checking sdram width x8 08h 15 minimum clock delay for back-to-back random column address t ccd = 1clk 01h 16 sdram device attributes : burst lengths supported 1, 2, 4, 8 & full page 8fh 17 sdram device attributes : # of banks on sdram device 4 banks 04h 18 sdram device attributes : cas latency 2 & 3 06h 19 sdram device attributes : cs latency 0 clk 01h 20 sdram device attributes : write latency 0 clk 01h 21 sdram module attributes non-buffered, non-registered & redundant addressing 00h 22 sdram device attributes : general +/- 10% voltage tolerance, burst read single bit write precharge all, auto precharge 0eh 23 sdram cycle time @cas latency of 2 10ns 12ns a0h c0h 2 24 sdram access time from clock @cas latency of 2 6ns 7ns 60h 70h 2 25 sdram cycle time @cas latency of 1 - - 00h 00h 26 sdram access time from clock @cas latency of 1 - - 00h 00h 27 minimum row precharge time (=t rp ) 20ns 20ns 14h 14h 28 minimum row active to row active delay (t rrd ) 20ns 20ns 14h 14h 29 minimum ras to cas delay (=t rcd ) 20ns 20ns 14h 14h 30 minimum activate precharge time (=t ras ) 50ns 50ns 32h 32h 31 module row density 1 row of 256mb 40h 32 command and address signal input setup time 2ns 2ns 20h 20h 33 command and address signal input hold time 1ns 1ns 10h 10h 34 data signal input setup time 2ns 2ns 20h 20h ? organization : 32mx72 ? composition : 32mx8 *9 ? used component part # : k4s560832b-tc1h/tc1l ? # of rows in module : 1 row ? # of banks in component : 4 banks ? feature : 1,375mil height & single sided component ? refresh : 8k / 64ms ? contents ;
serial presence detect pc100 unbuffered dimm rev 0.1 apr. 2000 byte # function described function supported hex value note -1h -1l -1h -1l 35 data signal input hold time 1ns 1ns 10h 10h 36~61 superset information (maybe used in future) - 00h 62 spd data revision code pc100 spd spec. ver. 1.2a 12h 63 checksum for bytes 0 ~ 62 - 4bh 7bh 64 manufacturer jedec id code samsung ceh 65~71 ...... manufacturer jedec id code samsung 00h 72 manufacturing location onyang korea 01h 73 manufacturer part # (memory module) m 4dh 74 manufacturer part # (dimm configuration) 3 33h 75 manufacturer part # (data bits) blank 20h 76 ...... manufacturer part # (data bits) 7 37h 77 ...... manufacturer part # (data bits) 4 34h 78 manufacturer part # (mode & operating voltage) s 53h 79 manufacturer part # (module depth) 3 33h 80 ...... manufacturer part # (module depth) 2 32h 81 manufacturer part # (refresh, # of banks in comp. & interface) 5 35h 82 manufacturer part # (composition component) 3 33h 83 manufacturer part # (component revision) b 42h 84 manufacturer part # (package type) t 54h 85 manufacturer part # (pcb revision & type) 0 30h 86 manufacturer part # (hyphen) " - " 2dh 87 manufacturer part # (power) c 43h 88 manufacturer part # (minimum cycle time) 1 1 31h 31h 89 manufacturer part # (minimum cycle time) h l 48h 4ch 90 manufacturer part # (tbd) blank 20h 91 manufacturer revision code (for pcb) 0 30h 92 ...... manufacturer revision code (for component) b-die (3rd gen.) 42h 93 manufacturing date (week) - - 3 94 manufacturing date (year) - - 3 95~98 assembly serial # - - 4 99~125 manufacturer specific data (may be used in future) undefined - 5 126 system frequency for 100mhz 100mhz 64h 127 pc100 specification details detailed 100mhz information afh adh 128+ unused storage locations undefined - 5 1. the bank select address is excluded in counting the total # of addresses. 2. this value is based on the component specification. 3. these bytes are programmed by code of date week & date year with bcd format. 4. these bytes are programmed by samsung s own assembly serial # system. all modules may have different unique serial #. 5. these bytes are undefined and can be used for samsung s own purpose. note :
serial presence detect pc100 unbuffered dimm rev 0.1 apr. 2000 m374s6453bt0-c1h/c1l byte # function described function supported hex value note -1h -1l -1h -1l 0 # of bytes written into serial memory at module manufacturer 128bytes 80h 1 total # of bytes of spd memory device 256bytes (2k-bit) 08h 2 fundamental memory type sdram 04h 3 # of row address on this assembly 13 0dh 1 4 # of column address on this assembly 10 0ah 1 5 # of module rows on this assembly 2 rows 02h 6 data width of this assembly 72 bits 48h 7 ...... data width of this assembly - 00h 8 voltage interface standard of this assembly lvttl 01h 9 sdram cycle time @cas latency of 3 10ns 10ns a0h a0h 2 10 sdram access time from clock @cas latency of 3 6ns 6ns 60h 60h 2 11 dimm configuration type ecc 02h 12 refresh rate & type 7.8us, support self refresh 82h 13 primary sdram width x8 08h 14 error checking sdram width x8 08h 15 minimum clock delay for back-to-back random column address t ccd = 1clk 01h 16 sdram device attributes : burst lengths supported 1, 2, 4, 8 & full page 8fh 17 sdram device attributes : # of banks on sdram device 4 banks 04h 18 sdram device attributes : cas latency 2 & 3 06h 19 sdram device attributes : cs latency 0 clk 01h 20 sdram device attributes : write latency 0 clk 01h 21 sdram module attributes non-buffered, non-registered & redundant addressing 00h 22 sdram device attributes : general +/- 10% voltage tolerance, burst read single bit write precharge all, auto precharge 0eh 23 sdram cycle time @cas latency of 2 10ns 12ns a0h c0h 2 24 sdram access time from clock @cas latency of 2 6ns 7ns 60h 70h 2 25 sdram cycle time @cas latency of 1 - - 00h 00h 26 sdram access time from clock @cas latency of 1 - - 00h 00h 27 minimum row precharge time (=t rp ) 20ns 20ns 14h 14h 28 minimum row active to row active delay (t rrd ) 20ns 20ns 14h 14h 29 minimum ras to cas delay (=t rcd ) 20ns 20ns 14h 14h 30 minimum activate precharge time (=t ras ) 50ns 50ns 32h 32h 31 module r ow density 2 rows of 256mb 40h 32 command and address signal input setup time 2ns 2ns 20h 20h 33 command and address signal input hold time 1ns 1ns 10h 10h 34 data signal input setup time 2ns 2ns 20h 20h ? organization : 64mx72 ? composition : 32mx8 *18 ? used component part # : k4s560832b-tc1h/tc1l ? # of rows in module : 2 rows ? # of banks in component : 4 banks ? feature : 1,375mil height & double sided component ? refresh : 8k / 64ms ? contents ;
serial presence detect pc100 unbuffered dimm rev 0.1 apr. 2000 byte # function described function supported hex value note -1h -1l -1h -1l 35 data signal input hold time 1ns 1ns 10h 10h 36~61 superset information (maybe used in future) - 00h 62 spd data revision code pc100 spd spec. ver. 1.2a 12h 63 checksum for bytes 0 ~ 62 - 4ch 7ch 64 manufacturer jedec id code samsung ceh 65~71 ...... manufacturer jedec id code samsung 00h 72 manufacturing location onyang korea 01h 73 manufacturer part # (memory module) m 4dh 74 manufacturer part # (dimm configuration) 3 33h 75 manufacturer part # (data bits) blank 20h 76 ...... manufacturer part # (data bits) 7 37h 77 ...... manufacturer part # (data bits) 4 34h 78 manufacturer part # (mode & operating voltage) s 53h 79 manufacturer part # (module depth) 6 36h 80 ...... manufacturer part # (module depth) 4 34h 81 manufacturer part # (refresh, # of banks in comp. & interface) 5 35h 82 manufacturer part # (composition component) 3 33h 83 manufacturer part # (component revision) b 42h 84 manufacturer part # (package type) t 54h 85 manufacturer part # (pcb revision & type) 0 30h 86 manufacturer part # (hyphen) " - " 2dh 87 manufacturer part # (power) c 43h 88 manufacturer part # (minimum cycle time) 1 1 31h 31h 89 manufacturer part # (minimum cycle time) h l 48h 4ch 90 manufacturer part # (tbd) blank 20h 91 manufacturer revision code (for pcb) 0 30h 92 ...... manufacturer revision code (for component) b-die (3rd gen.) 42h 93 manufacturing date (week) - - 3 94 manufacturing date (year) - - 3 95~98 assembly serial # - - 4 99~125 manufacturer specific data (may be used in future) undefined - 5 126 system frequency for 100mhz 100mhz 64h 127 pc100 specification details detailed 100mhz information ffh fdh 128+ unused storage locations undefined - 5 1. the bank select address is excluded in counting the total # of addresses. 2. this value is based on the component specification. 3. these bytes are programmed by code of date week & date year with bcd format. 4. these bytes are programmed by samsung s own assembly serial # system. all modules may have different unique serial #. 5. these bytes are undefined and can be used for samsung s own purpose. note :
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